next up previous
Next: Echelle Grating Stabilization Up: Payload System Improvements Previous: Flash Memory Data Storage

8.2.2 New Camera Electronics

  The electronics for the IMAPS camera was designed and built in the early 1980's. By today's standards it is power hungry (28w), employs too many electrical connectors, has an assortment of electrolytic capacitors that are 15 to 20 years old, and is spread over 8 circuit boards in three separate enclosures. Undoubtedly this detector would greatly benefit from present-day circuit integration.

The new camera design should enhance the reliability by having only 2 circuit boards located close to the CCD socket assembly. This greatly reduces the number of electrical connectors. The much higher level of integration of modern circuit components also reduces the number of discrete elements that must be connected together. The new electronics are largely divided between digital circuits (e.g. CCD clock generators) on one board and noise sensitive analog functions (e.g. video processor) on the other board.

Once again, flash memory technology is a key ingredient in our achievement of greater efficiency. We can realize an enormous consolidation of the CCD clocking control functions by coding them into the storage, rather than explicitly building them into circuitry. The old camera's 2 boards of sync generators have been essentially reduced to 2 flash memory chips with ancillary address and data mux logic. The flash memory stores the state of each sync signal for every sub-pixel cycle (60nS) in a full CCD frame period (67mS). A 16.66 MHz clock drives address logic which enables reads of the two 16 megabit flash memory chips at the IMAPS frame rate. The sync generator pattern is written into flash memory by the onboard micro-computer, and it can be reprogrammed (or refreshed) if necessary, even during the operation of IMAPS in orbit. In essence, the complexity of the sync generator has been moved from hardware to software, giving us a new flexibility that makes design and testing easier, as well as offering a capability to use CCDs with different characteristics (should we need to replace the CCD that is presently installed).

The CCD clock level and driver circuitry have been combined with the sync generator function onto the same board. An octal DAC (digital to analog converter) controlled by the onboard micro sets the CCD clock bias levels. The octal DAC replaces the less reliable mechanical potentiometers previously used to set the CCD clock levels and the DACs permit changes to be made remotely. The new CCD clock driver circuits utilize a recently introduced op-amp from Linear Technologies. These high slew rate op-amps are stable with large capacitive loads making them ideal for driving the CCD Clocks. Compared to the old clock drivers these op-amps will have lower power dissipation.


next up previous
Next: Echelle Grating Stabilization Up: Payload System Improvements Previous: Flash Memory Data Storage

12/15/1998